A laterally-diffused metal oxide semiconductor (LDMOS) transistor is a power device for high voltage, which has fast switching speed, high input impedance, low power consumption, and compatibility with a complementary metal oxide semiconductor (CMOS) process. Such a transistor is widely used for various power devices, including display driving integrated circuits (ICs), power converters, motor controllers, and power devices for cars. In the case of a power device, on-resistance (Ron) and breakdown voltage are important factors that have a significant impact on the performance of the device. Various techniques to maintain Ron and increase breakdown simultaneously have been suggested.
An LDMOS device can be used as a power device to drive a light-emitting diode (LED) device. In order to do so, it should maintain high breakdown and have low Ron simultaneously. To accomplish this, it is necessary to apply a Double Reduced Surface Field (RESULF) stacking a PTOP layer to a high voltage N WELL (HVNWELL).
FIG. 1 is a layout view of a general semiconductor device, for example, an LDMOS device. FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1 in the case of a related art power semiconductor device.
Referring to FIG. 2, a configuration of a related art LDMOS transistor includes an N-type doped deep well 2 and a P-type doped deep P well 3 in a P-type doped semiconductor substrate 1. A field insulating layer 42 having length W is formed on the surface of the N well 2, an N well 5 is formed in an open region at one side of the field insulating layer 42, and a drain region 24 doped with a high concentration N+ impurity is formed in the surface of the N well 5. A first P-TOP region 25 is formed in the deep N well 2 to form a RESULF structure.
Also, a P well 4 including inside portions of the deep P well 3 and the deep N well 2 is formed, and a second P-TOP region 12 including inside portions of the P well 4 and the deep N well 2 is formed. A source contact region 14 doped with a high concentration P+ impurity is formed in the surface of the second P-TOP region 12, and then, a source region 13 doped with a high concentration N+ impurity is formed in the second P-TOP region 12 adjacent to the source contact region 14. Then, a gate polysilicon 30 covering portions of the second P-TOP region 12 and the field insulating layer 42 is formed, and the gate polysilicon 30 is connected to an upper gate electrode 15 through wiring.
In an LDMOS device including a floating first P-TOP region of such a structure, since charges (i.e., electrons and holes) moved by an electric field are accumulated in the first P-TOP region, breakdown voltage decreases, so that it is necessary to change into a P-TOP structure that can be grounded in order to provide manufacturing process stability.
FIG. 3 is a cross-sectional view of an LDMOS device having a grounded P-TOP structure.
Referring to FIG. 3, the pitch of the first P-TOP region 25 is increased by a predetermined length, compared to that of the device shown in FIG. 2. Also, a high concentration P+ conductive connection region 18 is formed on the top surface of the increased first P-TOP region 25 to be connected to an upper ground line 19, and an extended gate polysilicon 30a and a gate electrode 15a are additionally formed.
In order to form the above structure, an additional space for expanding an existing gate poly is required. This increases a half pitch of a PTOP region and thus Ron increases. Therefore, the operating characteristics of an LDMOS device are affected.